1. Field of Invention
The techniques described herein relate to formation of a III-V semiconductor material (e.g., GaAsP) on a group IV semiconductor material (e.g., SiGe). Such techniques enable forming high-quality III-V semiconductor material having a low threading dislocation density suitable for formation of III-V devices.
2. Discussion of the Related Art
Integration of III-V compound thin films on silicon (Si) substrates has received significant attention for many years because of the potential to integrate III-V compound based semiconductor devices (e.g., photovoltaics, lasers, and high-speed transistors) with less expensive and more reliable Si technology. However, when considering the direct deposition of III-V compound materials on Si, challenges lie in the accommodation of lattice mismatch, thermal expansion mismatch and polar-nonpolar interfaces. Any one of these materials integration issues can result in the nucleation of debilitating defect densities.
A very small lattice mismatch (0.37% at 300° K) between gallium phosphide (GaP) and Si makes GaP the most suitable III-V material for direct epitaxial integration on Si. However, previous attempts over the last few decades have shown the presence of defects such as stacking faults (SF) and anti-phase boundaries (APB) in the GaP films. While recent work has indeed produced heteroepitaxially integrated GaP films on Si (100) substrates free of these interface-related defects via a carefully controlled nucleation methodology, such films do not currently possess dislocation densities low enough to enable the desired level of device performance, despite the low degree of lattice mismatch. In contrast, the analogous gallium arsenide/germanium (GaAs/Ge) interface has been demonstrated to be highly controllable, and under the proper conditions, low dislocation density GaAs without APBs and stacking faults can be grown epitaxially on Ge. Work by Sieg, et al. for molecular beam epitaxy (MBE), and Ting, et al. for metal-organic chemical vapor deposition (MOCVD), showed that the use of 6° offcut (100) Ge substrates combined with the proper surface annealing sequence, prior to the initiation of GaAs epitaxy in an appropriate temperature window, could produce reproducible, device-quality GaAs thin films on Ge. In contrast, the extreme sensitivity of the GaP/Si interface over a range of growth conditions tends to generally result in a three-dimensional island morphology with a high density of one or more types of microstructural defects, including stacking faults, threading dislocations and twins. Demonstration of an APB-free GaAsyP1-y/Si1-xGex interface showed that lattice-matched GaAsP films exhibit a 10×-100× higher threading dislocation density (TDD) due to dislocation nucleation at the heterovalent interface. Also, GaAsyP1-y TDD increases with increasing P content in the film.